The invention relates to Field Programmable Gate Arrays (FPGAs). More particularly, the invention relates to structures and methods for distributing high fan-out signals in FPGAs using the carry multiplexers provided in the FPGA configurable logic blocks (CLBs).
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth). CLBs typically include several logic cells, each including (for example) a function generator, a memory element such as a flip-flop or latch, and associated supporting logic.
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Routing resources (i.e., the programmable interconnect structure) can be a limiting factor in implementing user circuits in FPGAs. In other words, not only must the user logic elements fit into the available function generators and memory elements of the FPGA, but there must also be sufficient routing resources to properly interconnect these logic elements. The signals that use the most routing resources are typically those with the highest fan-out, that is, the signals with the largest number of destinations. Therefore, it is desirable to provide structures and methods that reduce the number of high fan-out signals distributed using the programmable interconnect structure in FPGAs.
The speed of interconnection paths between logic elements is often critical, as well. Routing delays often determine the maximum operating speed of a circuit, particularly the routing delays of the high fan-out signals. Therefore, it is also desirable to provide structures and methods that reduce the routing delays of high fan-out signals implemented in FPGAs.
The invention provides structures and methods that reduce interconnect resource usage and can reduce routing delays in FPGAs by routing high fan-out signals on the CLB carry chains.
A first embodiment of the invention provides a high fan-out signal distribution structure implemented in a Field Programmable Gate Array (FPGA). The FPGA includes an array of logic cells, each including a carry multiplexer. The carry multiplexers can be configured to form a carry chain. The carry chain logic is included in the FPGA in order to facilitate the implementation of multi-bit logic such as addition and subtraction. However, as described herein, the carry chain can also be used to distribute high fan-out signals by passing a high fan-out signal along the chain from carry-in terminal to carry-out terminal of each carry multiplexer, and tapping the signal at the carry-out terminals for distribution to a large number of destinations.
The advantages of this signal distribution structure include resource efficiency and routing speed. With regard to resource efficiency, the use of FPGA resources is minimized. Not only are function generators no longer needed to buffer the signal, but use of the general interconnect structure is also reduced. With regard to routing speed, passing the signal through the carry multiplexers is generally faster than the current practice of buffering the signal in function generators.
A second embodiment of the invention provides methods for distributing a high fan-out signal in an FPGA. The FPGA includes logic cells and an interconnect structure interconnecting the logic cells. The high fan-out signal is routed by configuring a series of logic cells to pass the high fan-out signal through carry multiplexers in a series of logic cells. The interconnect structure is configured to tap the carry-out signals from the carry multiplexers and distribute the carry-out signals to the various destinations.
As in the first embodiment, in this embodiment the carry multiplexers are simultaneously distributing the high fan-out signal and buffering the signal, without using any function generators and while reducing the use of the interconnect structure.